Title :
Delay testing using a matrix of accessible storage elements
Author :
Varma, Prab ; Gheewala, Tushar
Author_Institution :
CrossCheck Technol. Inc., San Jose, CA, USA
Abstract :
This paper discusses a delay test methodology that avoids the area and performance overhead of enhanced scan elements by using a matrix of accessible storage elements. Delay test generation is performed for circuits, which may contain internal tri-state elements, bi-directional ports, asynchronous sets/resets and clock gating, using an automatic test pattern generator that is based on an extended 16 valued calculus
Keywords :
VLSI; automatic test equipment; automatic test software; automatic testing; delays; fault diagnosis; integrated logic circuits; logic testing; ASIC; accessible storage elements; asynchronous sets/resets; automatic test pattern generator; bi-directional ports; clock gating; delay test generation; delay test methodology; enhanced scan elements; internal tri-state elements; matrix of accessible storage elements; performance overhead; Automatic testing; Calculus; Circuit faults; Circuit testing; Clocks; Design methodology; Integrated circuit testing; Propagation delay; Timing; Very large scale integration;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470696
