Reliability issues of using barrier-engineered (BE) tunneling dielectric for floating gate flash memories

Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a 1Mb test chip was fabricated to provide chip-level reliability understandings. Finally, these results are compared with barrier engineered charge-trapping (CT) devices. Our results suggest that BE FG device is not promising in terms of serious reliability degradation and tail bits. On the other hand, BE CT is more promising because it solves the erase and retention dilemma and it is naturally immune to tail bits due to the discrete trapped charge storage.