Bus-based integrated floorplanning

Author

Rafiq, Faran ; Chrzanowska-Jeske, Malgorzata ; Yang, Hannah Honghua ; Sherwani, N.

Author_Institution

Intel Microlectronics Services, Beaverton, OR, USA

Volume

2

fYear

2002

fDate

2002

Abstract

A new integrated floorplanning approach for bus-based designs is proposed. A bus consists of a set of wires that might be a logical, data or control, buses or just a bunch of wires that originate and terminate at the same modules. We simultaneously optimize topology of modules, optimize timing and perform bus planning to ensure the routability of the final floorplanning. Our floorplanner generates the location and shape for all interconnects, both, above and between the circuit blocks. By reducing a number of interconnects from nets to buses the approach is made feasible. Our experiments with MCNC benchmarks clearly show the superiority of integrated floorplanning approach over the classical floorplan-then-route approach. On an average 12-13% improvement in area as compared to traditional floorplanning algorithms has been achieved

Keywords

circuit layout CAD; circuit optimisation; integrated circuit interconnections; integrated circuit layout; network routing; timing; MCNC benchmarks; SOC type designs; bus planning; bus-based integrated floorplanning; integrated floorplanning approach; interconnect location; interconnect shape; microprocessor designs; mixed-integer-linear approach; module topology optimization; routability; timing optimization; Algorithm design and analysis; Constraint optimization; Cost function; Design optimization; Integrated circuit interconnections; Microprocessors; Routing; Timing; Topology; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1011493

Filename

1011493