A design synthesis system for DSP algorithms based on an optimal multiprocessor scheduler

This paper describes a design synthesis system which can generate a complete circuit specification efficiently for a given DSP algorithm based on an optimal multiprocessor scheduler. The design synthesis system is composed of two parts: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph (FSFG) as input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the design synthesis process with an example of a second order Gray-Markel lattice filter