Title :
Utilizing boundary scan to implement BIST
Author_Institution :
NCR, Wichita, KS, USA
Abstract :
The use of boundary scan as a cost effective design for test (DFT) technique for testing I/O interconnect type defects, i.e. solder opens/shorts, defective drivers/receivers, etc. is demonstrated. To gain added benefits for a small increase in circuit overhead, boundary scan provides an excellent foundation on which to implement a built-in self-test (BIST) strategy which allows migration into future products. This paper describes the BIST techniques and control implemented for two gate array designs at NCR - Peripheral Products Division (PPD)
Keywords :
boundary scan testing; built-in self test; design for testability; logic arrays; BIST; I/O interconnect; LFSR; MISR; Peripheral Products Division; boundary scan; circuit overhead; circular overhead; defective drivers/receivers; fault coverage; solder opens/shorts; two gate array designs; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Integrated circuit testing; Pins; Plastic packaging; Registers; System testing;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470705
