Utilizing boundary scan to implement BIST

The use of boundary scan as a cost effective design for test (DFT) technique for testing I/O interconnect type defects, i.e. solder opens/shorts, defective drivers/receivers, etc. is demonstrated. To gain added benefits for a small increase in circuit overhead, boundary scan provides an excellent foundation on which to implement a built-in self-test (BIST) strategy which allows migration into future products. This paper describes the BIST techniques and control implemented for two gate array designs at NCR - Peripheral Products Division (PPD)