Title :
Incremental placement algorithm for standard-cell layout
Author :
Li, Zhuoyuan ; Wu, Weimin ; Hong, Xianlong ; Gu, Jun
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
To satisfy timing constraints or complete clock net routing, it is sometimes necessary to make local modifications to circuits after placement. Redoing the time-consuming process of placement after each of these changes is no longer affordable. In this paper, we present a new algorithm W-ECOP to effect incremental changes on a standard cell layout automatically. This algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement algorithms usually do. Our method tries to minimize the adjustment on the initial placement and optimize the wirelength. Testing of W-ECOP on a group of practical test cases shows our algorithm can successfully accomplish incremental placement, with good quality and high speed
Keywords :
circuit layout CAD; circuit optimisation; constraint handling; integrated circuit interconnections; integrated circuit layout; minimisation; network routing; IC standard-cell layout; W-ECOP algorithm; cell layout automatic incremental changes; cell movement; clock net routing; placement adjustment minimization; post-placement local circuit modifications; row based cell insertion; timing constraints; wirelength optimization; wirelength-driven engineering change order placement algorithm; wirelength-driven incremental placement algorithm; Algorithm design and analysis; Clocks; Computer science; Integrated circuit layout; Iterative algorithms; Optimization methods; Routing; Testing; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location :
Phoenix-Scottsdale, AZ
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1011495