A full 2D and 3D TCAD simulation of ultimate 22nm NAND Flash memories

In this paper we propose a way to study the ultimate technological node for Flash cell described in the International Technology Roadmap for Semiconductors (ITRS), corresponding to the 22 nm feature size. We have first developed a 2D TCAD simulation of a 4-bit-NAND string based on classical microelectronics recipes, to validate the whole process conditions. To check the good behavior of our processed cells, we first evaluate the programmed and erased threshold voltages by electrically simulating the Drain Current versus Control Gate Voltage. Then we also investigate the impact of the short space between neighbor cells on disturb between cells inside the NAND string. We have developed a 3D TCAD simulation of a 3 × 3 array, based on the previous 2D process simulation, in order to extract the values of parasitic capacitances, disturbing the whole functioning of the array.