A VLSI inner-product processor for real-time DSP applications

A VLSI design of a 12×12-bit parallel inner-product processor (IPP) for two´s complement multiplication is presented. The designed architecture and its driving algorithm makes an efficient use of all the array cells in order to reduce the computation time. Therefore, the time-area complexity of the designed IPP is proportional to N×m²×T_FA for large N and is m times smaller than for a sequential computation on a single multiplier. An inner product of two N-dimensional vectors with m-bit words requires area proportional to m(m/2), and the delay time of (N+2m+log₂N)×T_FA, where T_FA denotes the delay of a full adder. The design has been fabricated in 2-μm CMOS double-metal technology. An example application of the designed IPP for solution of a triangular system is presented