Arithmetic acceleration techniques for wireless communication receivers

We develop techniques to accelerate the implementation of the next generation wireless communication algorithms in hardware. We discuss an implementation of a key computationally intensive baseband algorithm for joint multiuser channel estimation and detection for this purpose and study its real-time requirements. An analysis of the bottlenecks present in the algorithm is made. We present an acceleration technique using task decomposition to take advantage of the existing pipelining and parallelism flow in the algorithm. We show that an application specific system design with multiple processing elements is more effective than the conventional single processor approach as it can satisfy the high data rate requirements of the next generation wireless communication systems. Our analysis is done independent of the final mapping of the processing elements in hardware.