DocumentCode
1828248
Title
Truncated multiplication with approximate rounding
Author
Swartzlander, Earl E., Jr.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Volume
2
fYear
1999
fDate
24-27 Oct. 1999
Firstpage
1480
Abstract
In many signal processing applications it is desirable to maintain constant word size through the basic arithmetic operations of add, subtract, multiply and divide. Of these operations, multiply is the biggest concern as multiplying two n-bit data yields a 2n-bit product. Forming the full product and rounding it to the desired precision is mathematically attractive, but the complexity is high. Forming a portion of the bit product matrix would reduce the complexity, but this incurs potentially large errors. A compromise approach has been developed that represents a reasonable (in many applications) compromise. The complexity is slightly above that of a truncated bit product multiplier, but the accuracy is close to that of a rounded full precision multiplier.
Keywords
computational complexity; digital arithmetic; signal processing; approximate rounding; arithmetic operations; bit product matrix; complexity reduction; rounded full precision multiplier; signal processing applications; truncated bit product multiplier; truncated multiplication; Added delay; Adders; Application software; Circuits; Digital arithmetic; Hardware; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location
Pacific Grove, CA, USA
ISSN
1058-6393
Print_ISBN
0-7803-5700-0
Type
conf
DOI
10.1109/ACSSC.1999.831996
Filename
831996
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