Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds

Author

Maxwell, Peter C. ; Aitken, Robert C.

Author_Institution

Hewlett-Packard Co., Santa Clara, CA, USA

fYear

1993

fDate

17-21 Oct 1993

Firstpage

63

Lastpage

72

Abstract

In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation. If desired, the technique can also be used to predict actual voltages, which agree well with SPICE simulations. The approach is substantially faster than previous approaches for accurately simulating bridging faults

Keywords

CMOS integrated circuits; SPICE; fault diagnosis; fault location; integrated circuit testing; logic testing; CMOS bridging faults; SPICE simulations; benchmark; biased voting; bridge voltage; feedback; structure of transistors; threshold; variable gate logic thresholds; Bridge circuits; CMOS logic circuits; Circuit faults; Circuit simulation; Computational modeling; Logic gates; Semiconductor device modeling; Testing; Voltage; Voting;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1993. Proceedings., International

Conference_Location

Baltimore, MD

Print_ISBN

0-7803-1430-1

Type

conf

DOI

10.1109/TEST.1993.470717

Filename

470717