Title :
Efficient implementation of rounding units
Author :
Burgess, Neil ; Knowles, Simon
Author_Institution :
Div. of Electron., Cardiff Univ., UK
Abstract :
This paper shows how IEEE 754 floating-point standard compliant rounding may be merged with carry-propagate addition in high-performance FPU designs. The paper considers addition/subtraction, multiplication and divide/square root operations and demonstrates that in every case one parallel prefix adder with a small amount of additional logic is sufficient to cover all rounding modes.
Keywords :
adders; floating point arithmetic; IEEE 754 floating-point standard compliant rounding; addition/subtraction; carry-propagate addition; divide/square root operations; high-performance FPU design; multiplication; parallel prefix adder; rounding units implementation; Added delay; Adders; Arithmetic; Circuits; Electronic switching systems; Logic; Multiplexing; Propagation delay; Turning;
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
Conference_Location :
Pacific Grove, CA, USA
Print_ISBN :
0-7803-5700-0
DOI :
10.1109/ACSSC.1999.831998
