DocumentCode
1828279
Title
Fast and accurate CMOS bridging fault simulation
Author
Rearick, Jeff ; Patel, Janak H.
Author_Institution
Hewlett-Packard, Ft. Collins, CO, USA
fYear
1993
fDate
17-21 Oct 1993
Firstpage
54
Lastpage
62
Abstract
This paper identifies the two key factors involved in obtaining accurate bridging fault simulation results and presents a hybrid technique that maximizes both the speed and accuracy of bridging fault simulation for gate-level standard cell designs. Both combinational and sequential circuits are studied and the results are compared with several other bridging fault simulators
Keywords
CMOS integrated circuits; automatic testing; digital simulation; fault diagnosis; logic testing; CMOS bridging fault simulation; accuracy; combinational circuits; gate-level standard cell designs; hybrid technique; sequential circuits; speed; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Hybrid integrated circuits; Integrated circuit modeling; Logic circuits; Predictive models; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1993. Proceedings., International
Conference_Location
Baltimore, MD
Print_ISBN
0-7803-1430-1
Type
conf
DOI
10.1109/TEST.1993.470718
Filename
470718
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