Title :
Design of an ultra-low power SA-ADC with medium/high resolution and speed
Author :
Agnes, Andrea ; Bonizzoni, Edoardo ; Maloberti, Franco
Author_Institution :
Dept. of Electron., Univ. of Pavia, Pavia
Abstract :
Design strategies for power effective medium/high resolution Successive-Approximation ADC are discussed. The study considers reducing the power of the capacitive array with suitable capacitive attenuators that do not need using non-unity capacitors. The design of minimum power comparators is analyzed and a novel comparator scheme, named time-domain comparator, is described. The proposed methodologies, verified with a test design, is capable to provide 12-bit with 50-kHz signal band and 1-V supply. The achieved FoM is 14 fj/conv-level, which is well below the state-of-the-art.
Keywords :
analogue-digital conversion; comparators (circuits); integrated circuit design; low-power electronics; analog-digital converters; capacitive array; capacitive attenuators; frequency 50 kHz; power comparators; successive approximation; time-domain comparator; voltage 1 V; word length 12 bit; Approximation algorithms; Capacitance; Capacitors; Clocks; Energy consumption; Frequency; Logic; Sampling methods; Sensor arrays; Testing;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541339
