Title :
A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier
Author :
He Gong Wei ; U Fat Chio ; Sai Weng Sin ; Seng Pan U ; Martins, Rui P.
Abstract :
A power scalable 6-bit 1.2 GS/s flash Analog-to-Digital Converter (ADC) is designed in 90 nm CMOS. Rapid power on/off Track-and-Hold (T/H) and preamplifiers are proposed to provide scalable power consumption with sampling rate variation. Full transistor-level simulations of the ADC are presented from 1 MS/s (3 mW) to 1.2 GS/s (41 mW). At the maximum sampling rate the DNL is -0.9/+0.7 LSB and the INL is -0.8/+0.6 LSB. The ADC achieves 33 dB SNDR, 44 dB SFDR, and 0.9 pj/conversion-step at Nyquist from 1.2V power supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; preamplifiers; sample and hold circuits; CMOS; SFDR; SNDR; flash ADC; flash analog-to-digital converter; power consumption; power on/off track-and-hold; preamplifier; sampling rate variation; transistor-level simulations; Circuits; Clocks; Energy consumption; Latches; Preamplifiers; Sampling methods; Silicon compounds; Timing; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541340
