• DocumentCode
    1828391
  • Title

    A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration

  • Author

    Hee-Cheol Choi ; Young-Ju Kim ; Se-Won Lee ; Jae-Yeol Han ; Oh-Bong Kwon ; Younglok Kim ; Seung-Hoon Lee

  • Author_Institution
    Dept. of Electron. Eng., Sogang Univ., Seoul
  • fYear
    2008
  • fDate
    18-21 May 2008
  • Firstpage
    9
  • Lastpage
    12
  • Abstract
    This work describes a 12 b 120 MS/s dual-channel SHA-free Nyquist ADC based on a mid-code calibration technique eliminating offset mismatch between channels. The prototype ADC achieves a peak SNDR of 61.1 dB and a peak SFDR of 74.7 dB for input frequencies up to 60 MHz at 120 MS/s. Also, the measured DNL and INL are within plusmn0.30 LSB and plusmn0.95 LSB, respectively. The ADC fabricated in a 0.13 mum CMOS process occupies an active die area of 0.56 mm and consumes and consumes 51.6 mW.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; calibration; high-speed integrated circuits; signal sampling; ADC fabrication; CMOS process; INL; SFDR; SHA-free dual-channel Nyquist ADC; measured DNL; mid-code calibration technique; offset mismatch elimination; power 52 mW; size 0.13 mum; voltage 1.2 V; Calibration; Clocks; Computational Intelligence Society; Design engineering; Frequency; Pipelines; Prototypes; Sampling methods; Signal resolution; Signal sampling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    978-1-4244-1684-4
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4541341
  • Filename
    4541341
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1828391