• DocumentCode
    1828588
  • Title

    A Performance Study of Traversing Spatial Indexing Structures in Parallel on GPU

  • Author

    Kim, Jinwoong ; Hong, Sumin ; Nam, Beomseok

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Ulsan Nat. Inst. of Sci. & Technol., Ulsan, South Korea
  • fYear
    2012
  • fDate
    25-27 June 2012
  • Firstpage
    855
  • Lastpage
    860
  • Abstract
    CUDA is a parallel programming environment that enables significant performance improvement by leveraging the massively parallel processing capability of the GPU. Inherently spatial indexing structures such as R-Trees are not well suited for CUDA environment due to its irregular tree traversal for range queries. Traversing irregular tree search paths makes it hard to maximize the utilization of many-core architectures. In this paper, we propose assigning an individual sub-tree to each SMP (streaming multi-processor) in GPGPU, such that CUDA cores in the same SMP co-operate to navigate tree index nodes. This parallel partitioned-indexing improves the utilization of many cores in GPGPU significantly. Also, we propose a new range query search algorithm - three-phase-search that avoids non-sequential random access to tree nodes and accelerates the search performance of spatial indexing structures on GPU. Our experimental results show that GPU-based parallel spatial indexing scheme on NVIDA Tesla M2090 GPGPU outperforms the CPU-based multi-threaded R-trees on AMD Opteron 6128HE processor by two times.
  • Keywords
    graphics processing units; indexing; multiprocessing systems; parallel architectures; performance evaluation; query processing; search problems; trees (mathematics); AMD Opteron 6128HE processor; CUDA environment; GPGPU; GPU-based parallel spatial indexing scheme; Jinwoong parallel programming environment; NVIDA Tesla M2090 GPGPU; SMP; individual subtree; manycore architectures; nonsequential random access; parallel partitioned indexing; parallel processing capability; range query search algorithm; search performance; streaming multiprocessor; three-phase search; traversing spatial indexing structures; tree index nodes; Graphics processing unit; Indexing; Instruction sets; Memory management; Parallel processing; GPGPU indexing; Multi-dimensional indexing; Multi-dimensional range query;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on
  • Conference_Location
    Liverpool
  • Print_ISBN
    978-1-4673-2164-8
  • Type

    conf

  • DOI
    10.1109/HPCC.2012.121
  • Filename
    6332259