Title :
Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric
Author :
Khan, M.M. ; Navaridas, Javier ; Rast, A.D. ; Jin, X. ; Plana, L.A. ; Luján, M. ; Woods, J.V. ; Miguel-Alonso, J. ; Furber, S.B.
Author_Institution :
Sch. of Comput. Sci., Univ. of Manchester, Manchester, UK
fDate :
June 30 2009-July 4 2009
Abstract :
Configuring a million-core parallel system at boot time is a difficult process when the system has neither specialised hardware support for the configuration process nor a preconfigured default state that puts it in operating condition. SpiNNaker is a parallel chip multiprocessor (CMP) system for neural network (NN) simulation. Where most large CMP systems feature a sideband network to complete the boot process, SpiNNaker has a single homogeneous network interconnect for both application inter-processor communications and system control functions such as boot load and run-time user-system interaction. This network improves fault tolerance and makes it easier to support dynamic run-time reconfiguration, however, it requires a boot process that is transaction-level compatible with the application´s communications model. Since SpiNNaker uses event-driven asynchronous communications throughout, the loader operates with purely local control: there is no global synchronisation, state information, or transition sequence. A novel two-stage ldquounfoldingrdquo boot-up process efficiently configures the SpiNNaker hardware and loads the application using a high-speed flood-fill technique with support for run-time re-configuration. SystemC simulation of a multi-CMP SpiNNaker system indicates an error-free CMP configuration time of 1.3 ms, while a high-level simulation of a full-scale system (64 K CMPs) indicates a mean application-loading time of ~20 ms (for a 100 KB application), which is virtually independent of the size of the system. We verified the CMP configuration process with hardware-level Verilog simulation.
Keywords :
asynchronous circuits; fault tolerant computing; microprocessor chips; multiprocessor interconnection networks; neural nets; parallel processing; reconfigurable architectures; SpiNNaker; SystemC simulation; application interprocessor communication; application loading; boot load; dynamic run-time reconfiguration; event-driven asynchronous communication; event-driven configuration; fault tolerance; high-speed flood-fill technique; homogeneous interconnect fabric; homogeneous network interconnect; million-core parallel system; neural network simulation; parallel chip multiprocessor system; run-time user-system interaction; system control function; two-stage unfolding boot-up process; Biological system modeling; Communication system control; Concurrent computing; Control systems; Fabrics; Hardware; Neural networks; Neurons; Parallel processing; Runtime; Chip Multiprocessor; Embedded Systems; Fault-tolerance; Massively Parallel Computing; Multi-CMP Configuration; Neural Networks; Real-time Application;
Conference_Titel :
Parallel and Distributed Computing, 2009. ISPDC '09. Eighth International Symposium on
Conference_Location :
Lisbon
Print_ISBN :
978-0-7695-3680-4
DOI :
10.1109/ISPDC.2009.25