DocumentCode
1828834
Title
A reconfigurable multi-stage frequency response masking filter bank architecture for software defined radio receivers
Author
Smitha, K.G. ; Mahesh, R. ; Vinod, A.P.
Author_Institution
Sch. of Comput. EngineeringNanyang Technol., Univ. Nanyang, Singapore
fYear
2008
fDate
18-21 May 2008
Firstpage
85
Lastpage
88
Abstract
The most computationally demanding part in the digital front-end of a Software radio receiver is the channelizer, which operates at the highest sampling rate. The channelizer extracts multiple narrowband channels from the digitized wideband input signal. The limitation of the conventional uniform Discrete Fourier transform (DFT) filter bank channelizer is that, it is incapable of extracting channels of multiple bandwidths, as the prototype filter has fixed equal bandwidths. Reconfigurable filter bank architecture for the SDR channelizer, based on multi-stage frequency response masking technique is proposed in this paper. The proposed architecture is capable of extracting channels with different bandwidths corresponding to different wireless communication standards. Design examples show that proposed architecture offers a complexity reduction of 97.2 % over the conventional Per-Channel (PC) approach and DFT filter banks.
Keywords
digital filters; discrete Fourier transforms; radio receivers; software radio; discrete Fourier transform; filter bank channelizer; multistage frequency response masking technique; software defined radio receiver; Bandwidth; Computer architecture; Discrete Fourier transforms; Filter bank; Frequency response; Narrowband; Receivers; Sampling methods; Software radio; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-1683-7
Electronic_ISBN
978-1-4244-1684-4
Type
conf
DOI
10.1109/ISCAS.2008.4541360
Filename
4541360
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