Prototyping of low-cost wafer level packages

WLP with various design configurations is fast becoming a common package for high performance applications. Besides large-die or embedded WLPs in System-in-Package, technology development in the industry also focuses on cost-effective WLP with acceptable level of functional and reliability performances, suitable for low-pin-count or small-die applications. Nepes is developing a series of low-cost wafer level packages (LCWLPs) to address the cost and technology demands. This paper will focus on prototyping of a non-UBM LCWLP with RDL, to be used as a baseline for relative cost, functional and reliability performances comparison with conventional WLPs and future LCWLPs of the same die sizes and ball layout. Previously, simulations were performed to confirm good electrical, mechanical (warpage and thermal cycling) and thermal performances of LCWLP. Here, process development is carried out to fabricate prototype of LCWLP. Several process issues are successfully resolved. Subsequently, LCWLP is qualified under package level reliability tests, including multi-reflow, solder shear/pull tests, pressure cooker test (PCT), and high temperature storage (HTS) test. After package level qualification, effort will be spent on board level tests. Here, board level drop test simulations are conducted for 3 different sizes of LCWLP. They are shown to have reasonable drop test performance, comparable to typical BGAs.