VLSI design of a processor for an integrated massively parallel architecture

This massively parallel machine is an original approach which takes the most of possibilities of VLSI and stands halfway between the Connection Machine and 32-bit processor based hypercubes. It is implemented as an MIMD array of cells communicating by message passing; each cell includes a simple programmable processor with a small amount of RAM and a parallel wormhole based routing part. The authors are interested in the class of irregular algorithms which enable each elementary processor to run a proper task and communicate with others according to an irregular topology. Some examples are logical simulation, placement, neural net emulation, ... . After introducing the global structure of the architecture, the various communication problems encountered in massively parallel architectures and the present approach to solve them, the authors propose an original wormhole based routing system able to forward up to five messages in parallel. They then focus on the basic cell itself by presenting the specifications of the processor. They finish by describing the whole cell VLSI design and the performances obtained with respect to transputer and Connection Machine chips