Title :
Improving the power-delay product in SCL circuits using source follower output stage
Author :
Tajalli, Armin ; Gurkaynak, Frank K. ; Leblebici, Yusuf ; Alioto, Massimo ; Brauer, Elizabeth J.
Author_Institution :
Microelectron. Syst. Lab. (LSM), Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne
Abstract :
This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra- low power applications. Designed in conventional digital 0.18mum CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.
Keywords :
CMOS logic circuits; buffer circuits; integrated circuit modelling; low-power electronics; CMOS technology; current 10 nA; low power electronics; power-delay product; size 0.18 mum; source coupled logic circuits; source follower buffers; voltage 0.6 V; CMOS logic circuits; CMOS technology; Capacitance; Coupling circuits; Energy consumption; Logic circuits; MOS devices; Tail; Threshold voltage; Voltage control;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541375
