FPGA implementation of A MASH 1-1-1 delta-sigma modulator infractional-N phase locked loop for fuzzy control application

A digital third-order MASH 1-1-1 delta-sigma (ΔΣ) modulator (DSM) is designed and implemented on field programmable gate array (FPGA) customer board (Lyrtech) in fractional-N phase-locked loop (PLL). Fractional-N frequency synthesizers have many advantages over their conventional counterparts, integer-N synthesizers. These include, among others, high frequency resolution, fast channel switching speed, low in-band phase noise, less stringent phase noise requirement on the external VCOs, permitting direct digital modulation. Verilog is adopted in this study for describing MASH 1-1-1. Simulations by Xilinx and Simulink and measurements with oscilloscope and logic analyzer are performed to verify our discussion and the results are pretty matched.