A unified architectural tradeoff methodology

Presents a unified approach to assess the tradeoff of architecture techniques that affect mean memory access time. The architectural features considered include cache hit ratio, processor stalling features, line size, memory cycle time, the external data bus width of a processor, pipelined memory system, and read bypassing write buffers. The authors demonstrate how each of these features can be traded off to achieve the desired performance. The performance of an architecture feature is quantified in terms of cache hit ratio based on the equivalence of mean memory delay time. They investigate the implication of architectural tradeoffs on the pin count, memory system design, and on-chip cache area for microprocessor systems