A high performance GaAs gate array family

Author

Lee, G. ; Canaga, S. ; Terrell, B. ; Deyhimy, I.

Author_Institution

Vitesse Semicond. Corp., Camarillo, CA, USA

fYear

1989

fDate

22-25 Oct. 1989

Firstpage

33

Lastpage

36

Abstract

Power dissipation is a design limiting factor in many high-performance systems. A GaAs gate array family that can directly replace ECL with equivalent speed performance at one quarter the power dissipation is presented. The arrays have been developed in three sizes with 3 K, 5 K, and 15 K logic gates. The I/O buffers have been designed to be compatible with ECL, TTL, or GaAs. The objective of this work is to describe gate array design features and discuss the measured performance as compared to ECL.<>

Keywords

III-V semiconductors; Schottky gate field effect transistors; cellular arrays; field effect integrated circuits; gallium arsenide; logic arrays; DCFL; GaAs gate array family; MESFET devices; Vitesse E/D process; compatible I/O buffers; direct-coupled FET logic; high-performance systems; monolithic IC; power dissipation; Circuit testing; Clocks; Design automation; Gallium arsenide; Integrated circuit interconnections; Logic arrays; Logic gates; MOS devices; Power dissipation; Thermal management;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/GAAS.1989.69287

Filename

69287