An Analytical Approach to Modeling and Evaluation of Optical Chip-scale Network using Stochastic Network Calculus

Optical networks have recently been proposed for chip-scale communication on high performance manycore chips by leveraging their notable advantages in bandwidth and power-efficiency. The design of optical network on-chip (NoC) is characterized by challenging trade-offs among latency, throughput, energy consumption, and silicon area requirements. These trade-offs are conventionally studied using simulations which become computationally expensive, especially for complex optical NoCs. In this paper, we present an analytical approach based on stochastic network calculus (SNC) to model and evaluate chip-scale optical networks. SNC is a new theory dealing with queuing type problems, which provides an elegant framework for computer network analysis. Our work applies the stochastic network calculus theory on chip-scale optical burst-switched interconnection network. We develop SNC models for the edge node to estimate on-chip memory requirements and calculating end-to-end network latency. Furthermore, we propose a "virtual wavelength buffer" model to study the wavelength requirements with respect to a tolerable burst loss probability. These analytical models can be used to rapidly dimension system resources requirements and performance bounds, which are essential for early-stage network design. Cycle-accurate simulation results verify that our analytical bounds are tight, which means that our SNC-based approach can provide useful system-level guidelines for optical chip-scale network design.