Implementation and analysis of VCO based power-clock supply generator

Demands for low power electronics have motivated designers to explore new approaches to VLSI circuits. The classical approaches of reducing energy dissipation in conventional CMOS circuits include reducing the supply voltages, node capacitances, and switching frequencies. Energy-recovery circuitry, on the other hand, is a new promising approach to the design of VLSI circuits with very low energy dissipation. The supply voltage in adiabatic circuits in addition to providing the power to the circuit behaves as the clock of the circuit and for this reason is called power clock. One of the main concerns in the adiabatic logic circuits is the power clock generation. The design of a power clock generator is a challenging problem in this field. This paper discusses the design and simulation results of a VCO based power-clock supply generation for quasi-adiabatic circuits. The analysis is carried out in cadence design environment using 180 nm technology using cell based design approach.