A 10 Gb/s optical receiver in 0.25 μm silicon-on-sapphire CMOS

Author

Chen, Paul C P ; Pappu, Anand M. ; Fu, Zhongtao ; Wattanapanitch, Woradorn ; Apsel, Alyssa B.

Author_Institution

Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY

fYear

2008

fDate

18-21 May 2008

Firstpage

193

Lastpage

196

Abstract

An optical receiver designed and fabricated in 0.25 mum ultra-thin silicon (UTSi) on sapphire technology is flip-chip integrated with p-i-n photodiodes. The receiver includes a transimpedance amplifier (TIA), limiting amplifiers (LA), and an output buffer. The power consumption of the TIA and limiting amplifiers is 67.3 mW. The receiver is shown operating with a gain of 57 dBOmega at a bit rate of 10 Gb/s. The measured sensitivity is -1.7 dBm for a bit error rate of 10^-9. This is the first 0.25 mum CMOS TIA and LA codesign that operates optically at 10 Gb/s.

Keywords

CMOS integrated circuits; amplifiers; error statistics; flip-chip devices; optical receivers; p-i-n photodiodes; sapphire; silicon-on-insulator; Si; bit error rate; flip-chip; limiting amplifiers; optical receiver; p-i-n photodiodes; sapphire technology; silicon-on-sapphire CMOS; transimpedance amplifier; ultra-thin silicon; Bit rate; CMOS technology; Energy consumption; Optical amplifiers; Optical buffering; Optical design; Optical receivers; PIN photodiodes; Power amplifiers; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4244-1683-7

Electronic_ISBN

978-1-4244-1684-4

Type

conf

DOI

10.1109/ISCAS.2008.4541387

Filename

4541387