• DocumentCode
    1829996
  • Title

    Evaluating stream buffers as a secondary cache replacement

  • Author

    Palacharla, Subbarao ; Kessler, R.E.

  • Author_Institution
    Dept. of Comput. Sci., Wisconsin Univ., Madison, WI, USA
  • fYear
    1994
  • fDate
    18-21 Apr 1994
  • Firstpage
    24
  • Lastpage
    33
  • Abstract
    Today´s commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast data access via a large secondary cache. But large secondary caches can be expensive, particularly in large-scale parallel systems with many processors (and thus many caches). The authors evaluate a memory system design that can be both cost-effective as well as provide better performance, particularly for scientific workloads: a single level of (on-chip) cache backed up only by Jouppi´s stream buffers and a main memory. This memory system requires very little hardware compared to a large secondary cache and doesn´t require modifications to commodity processors. The authors use trace-driven simulation of fifteen scientific applications from the NAS and PERFECT suites in their evaluation. They present two techniques to enhance the effectiveness of Jouppi´s original stream buffers: filtering schemes to reduce their memory bandwidth requirement and a scheme that enables stream buffers to prefetch data being accessed in large strides. The results show that, for the majority of the benchmarks, stream buffers can attain hit rates that are comparable to typical hit rates of secondary caches. Also, the authors find that as the data-set size of the scientific workload increases the performance of streams typically improves relative to secondary cache performance, showing that streams are more scalable to large data-set sizes
  • Keywords
    buffer storage; memory architecture; performance evaluation; filtering schemes; high sustained performance; low latency memory system; memory bandwidth requirement; memory system design; on-chip cache; performance; secondary cache; secondary cache performance; stream buffers; trace-driven simulation; Bandwidth; Costs; Hardware; High performance computing; Large-scale systems; Microprocessors; Prefetching; Random access memory; System-on-a-chip; Workstations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 1994., Proceedings the 21st Annual International Symposium on
  • Conference_Location
    Chicago, IL
  • Print_ISBN
    0-8186-5510-0
  • Type

    conf

  • DOI
    10.1109/ISCA.1994.288164
  • Filename
    288164