VLSI architecture for data-reduced steering matrix feedback in MIMO systems

Beamforming (BF) for multiple-input multiple-output (MIMO) wireless communications systems can improve the error rate performance by spatial separation of the transmitted data streams. BF requires to feed back steering matrices from the receiver to the transmitter. The usually large amount of feedback data asks for data reduction schemes. In this paper, we investigate the error rate performance/feedback rate trade-off associated with steering matrix data-reduction schemes and present a corresponding hardware-optimized compression/decompression architecture. Our VLSI implementation achieves up to 50% data reduction for 4times4-dimensional steering matrices without a significant decrease in terms of error rate performance at a circuit complexity of only 7 k gate equivalents.