Architectural Implications for SIMD Processors in the Wireless Communication Domain

To further improve the performance of SIMD (Single Instruction Multiple Data) architectures, which are widely used in the wireless communication domain. The main components of Long Term Evolution (LTE) protocol are analyzed. Performance investigation is taken on a cycle-accurate simulator, featuring the main characteristics of existing SIMD architectures. Based on the investigation, three insightful architectural implications, including the concurrent execution of scalar and parallel processing, multiple sub-matrixes accessible matrix register file, and bidirectional shuffle unit are proposed. The experiment result shows that an average of 30% performance gain can be achieved by the SIMD architecture enhanced with the proposed implications. The hardware cost of these implications is also discussed.