Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

Author

Reum Oh ; Byunghyun Lee ; Sang-Woong Shin ; Wonil Bae ; Hundai Choi ; Indal Song ; Yun-Sang Lee ; Jung-Hwan Choi ; Chi-Wook Kim ; Seong-Jin Jang ; Joo Sun Choi

Author_Institution

Memory Div., Samsung Electron., Hwasung, South Korea

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

For the demand of sever systems with high performance, high density and low power consumption, 3-D DDR4 SDRAM with TSVs was developed. In order to achieve higher data rate at lower voltage in comparison with precedent DDR3 SDRAM with TSVs, the placements of TSVs have been optimized without the penalty of chip size and the calibration method for reducing process mismatch between stacked DRAM chips is proposed. Additionally, new cell test method for stacked dies is adopted to keep costs down and the skewed self-refresh is proposed to reduce power noise. The IO speed of new DDR4 SDRAM with TSVs is increased to 2.4Gb/s at 1.2V.

Keywords

DRAM chips; integrated circuit design; integrated circuit testing; low-power electronics; three-dimensional integrated circuits; 3D DDR4 SDRAM; cell test method; design technologies; low power consumption; power noise reduction; sever systems; skewed self-refresh; stacked DRAM chips; stacked dies; voltage 1.2 V; Calibration; Clocks; Delays; Power demand; SDRAM; Through-silicon vias; DRAM; TSV; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858367

Filename

6858367