A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package

The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms WIO2 with TSV in terms of area efficiency (4x better) and manufacturing cost (40% cheaper) and outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness.