Design target exploration for meeting time-to-market using pareto analysis

Early design phase space exploration, power validation and performance estimation will enable faster design convergence and shorter time-to-market. System level models based on physical design parameters, in-situ macro models and background SPICE simulation improves overall model accuracy. This paper describes a pareto analysis methodology for design target generation to meet time-to-market constraint; illustrating design choice generation algorithm and a test circuit SPICE validation. Power and performance centric design solutions (targets) that are not obvious to the designers are explored. Pareto analysis yielded power centric design target that improved both system power consumption and performance by 19.6% and 6.3% respectively. Performance centric design target improved system level performance and power by 11.7% and 1.63% respectively.