Input port reduction for efficient substrate extraction in large scale IC’s

A methodology is proposed to improve the efficiency of the substrate impedance extraction process for a large scale circuit by exploiting the circuit activity. Similarly biased regions of the substrate short-circuited by the ground network are identified to reduce the computational complexity of the extraction process. Each of these voltage domains is represented by a single equivalent input port to the substrate, merging the remaining ports within that domain. An algorithm is presented to determine these domains and generate an equivalent port for each domain. The parasitic impedance of the ground network is updated to maintain accuracy. A reduction of more than two orders of magnitude in the number of extracted substrate resistances is demonstrated while introducing 15% error in the rms value of the substrate noise voltage at the sense node.