Low variation current source for 90nm CMOS

We investigate an addition-based current source that reduces the impact of process variation and device mismatch without post-fabrication efforts. By optimizing the transistor size and taking the advantage of the nonlinearity associated with real resistors in 90 nm CMOS technology, we are able to achieve significant performance improvement. Simulation based on the proposed circuit topology shows more than 67% reduction in the current variation of an equally sized single transistor current source.