Integrated quadrupler circuit in coplanar technology for 60 GHz wireless applications

This paper describes the design, the simulation and the measured results of a frequency quadrupler (/spl times/4 multiplier) circuit for mm-wave applications. The coplanar circuit was designed in a balanced configuration which makes it extremely small in area while maintaining excellent performance. A large number of circuits from several wafers were measured. The conversion loss is 4 dB and the harmonic suppression >20 dB with 6 dBm input power.