ASIP-based Design and Implementation of RSA for Embedded Systems

The RSA public-key cryptosystem is widely used to provide security protocols and services in the network communication. However, design and implementation of the RSA cryptosystem to meet the real-time requirements of embedded applications are challenging issues, due to the computation intensive characteristics of the RSA arithmetic operations and the limited resources in the embedded systems. Various implementation and optimization methods have been proposed for RSA algorithm. However, software execution of RSA on general-purpose processors usually suffers from slow execution speed; while application-specific integrated circuit (ASIC) based approaches are lack of flexibility. In this work, we present a systematic design approach of application-specific instruction-set processor(ASIP) for the RSA cryptographic algorithm. We identify and optimize the custom instructions in the RSA algorithm, and extend the instruction set architecture (ISA) of a standard 32-bit RISC processor to accommodate them. We employ the Electronic System Level (ESL) methodology in the development of the proposed ASIP in the Xilinx Virtex5 LX110T FPGA platform. Compared to the original RISC ISA, our extended ASIP achieves approximate 2.69 times performance improvement with only 25.6% more resource required.