A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver

Author

Chi-Cheng Ju ; Tsu-Ming Liu ; Huaide Wang ; Yung-Chang Chang ; Chih-Ming Wang ; Chang-Lin Hsieh ; Liu, B. ; Hue-Min Lin ; Chia-Yun Cheng ; Chun-Chia Chen ; Min-Hao Chiu ; Sheng-Jen Wang ; Ping Chao ; Hu, M.J. ; Yeh, Ryan ; Chuang, Tsung-Yen ; Hsiu-Yi Lin

Author_Institution

Mediatek Inc., Hsinchu, Taiwan

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression processor (LCP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. The proposed TV SoC processor includes multi-standard 4K×2K@60fps playback and 3.4Gbps HDMI receiver (Rx), and both scenario dissipate 198.15mW at 1.2V core and 3.3V I/O.

Keywords

CMOS digital integrated circuits; digital television; error compensation; system-on-chip; television receivers; CMOS process; ECP; LCP; bit rate 3.4 Gbit/s; digital TV SoC processor; efficiency 34.3 percent; efficiency 38.5 percent; error compensation processor; integrated HDMI-MHL receiver; lossless compression processor; memory management unit design; multistandard TV SoC processor; power 198.15 mW; resource sharing technique; size 40 nm; visual quality; voltage 1.2 V; voltage 3.3 V; Decoding; Error compensation; Receivers; Standards; Streaming media; System-on-chip; TV;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858389

Filename

6858389