• DocumentCode
    183104
  • Title

    A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with −106dBc/Hz In-band noise using time amplifier based TDC

  • Author

    Elkholy, Ahmed ; Anand, Tejasvi ; Woo-Seok Choi ; Elshazly, Amr ; Hanumolu, Pavan Kumar

  • Author_Institution
    Univ. of Illinois, Urbana, IL, USA
  • fYear
    2014
  • fDate
    10-13 June 2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    A digital fractional-N PLL that employs a time amplifier based TDC and a truly fractional divider to achieve low in-band noise with a wide bandwidth of 3MHz is presented. Fabricated in 65nm CMOS process, the prototype PLL consumes 3.7mW at 4.5GHz output frequency and achieves better than -106dBc/Hz in-band noise and 490fsrms integrated jitter. This translates to a FoMJ of -240.5dB, which is the best among the reported fractional-N PLLs.
  • Keywords
    CMOS digital integrated circuits; MMIC amplifiers; digital phase locked loops; field effect MMIC; time-digital conversion; CMOS process; FoM; bandwidth 3 MHz; digital fractional-N PLL; frequency 4.5 GHz; integrated jitter; low in-band noise; power 3.7 mW; size 65 nm; time 490 fs; time amplifier based TDC; truly fractional divider; Frequency measurement; Jitter; Phase frequency detector; Phase locked loops; Phase noise; Quantization (signal);
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits Digest of Technical Papers, 2014 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4799-3327-3
  • Type

    conf

  • DOI
    10.1109/VLSIC.2014.6858391
  • Filename
    6858391
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=183104