A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS

Author

Jun Yin ; Luong, Howard C.

Author_Institution

Hong Kong Univ. of Sci. & Technol., Hong Kong, China

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

Employing a switched-transformer-based triple-band Q-VCO and a magnetically-tuned multi-mode triple-push x4 injection-locked frequency multiplier (ILFM), a CMOS SDR frequency synthesizer generates IQ LO signals continuously from 0.37GHz to 23.25GHz and differential LO signals from 23.25GHz to 46.5GHz. Implemented in 65-nm CMOS, the synthesizer measures phase noise of -94dBc/Hz in band and of -136dBc/Hz at 10MHz offset from 7.2GHz and RMS jitters between 0.43ps and 0.55ps across the whole frequency range while consuming 36 to 90mW and occupying an active area of 1.82mm².

Keywords

CMOS integrated circuits; MMIC frequency convertors; MMIC oscillators; UHF frequency convertors; UHF integrated circuits; UHF oscillators; field effect MIMIC; field effect MMIC; frequency multipliers; frequency synthesizers; injection locked oscillators; millimetre wave frequency convertors; millimetre wave oscillators; software radio; transformers; voltage-controlled oscillators; CMOS SDR frequency synthesizer; CMOS process; ILFM; RMS jitters; differential LO signals; frequency 0.37 GHz to 46.5 GHz; magnetically-tuned multimode triple-push x4 injection-locked frequency multiplier; power 36 mW to 90 mW; size 65 nm; software-defined radios; switched-transformer-based triple-band Q-VCO; time 0.43 ps to 0.55 ps; CMOS integrated circuits; Frequency measurement; Frequency synthesizers; Noise measurement; Phase measurement; Phase noise; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858394

Filename

6858394