Title :
Design of a low-cost VLSI architecture for 1.6 kbps speech synthesis
Author :
Yu, Chu ; Hu, Hwai-Tsu
Author_Institution :
Dept. of Electron. Eng., Nat. I-Lan Inst. of Technol., Taiwan
Abstract :
We present a low-cost architecture for speech synthesis at 1.6 kbps. The speech synthesis algorithm is formulated in terms of a hardware-oriented design. Based on our proposed speech vocoder, the novel architecture consumes lower hardware resources and is therefore suited for hardware implementation.
Keywords :
VLSI; hardware-software codesign; speech coding; speech synthesis; vocoders; 1.6 kbit/s; hardware-oriented design; low-cost VLSI architecture; speech coding; speech synthesis; vocoder; Algorithm design and analysis; Computer architecture; Filters; Hardware; Signal analysis; Speech analysis; Speech coding; Speech synthesis; Very large scale integration; Vocoders;
Conference_Titel :
Consumer Electronics, 2003. ICCE. 2003 IEEE International Conference on
Print_ISBN :
0-7803-7721-4
DOI :
10.1109/ICCE.2003.1218910
