Impact of Instruction Cache and Different Instruction Scratchpads on the WCET Estimate

Hard real-time systems demand high performance, but also tight WCET estimates. The tightness of the WCET estimates strictly depends on the WCET analysis of the memory system. In this paper we quantify the impact of different instruction memories on the WCET estimates. A function-based dynamic scratchpad, a cache, and static scratchpads are compared. Furthermore, we inspect the pessimism introduced by memory access interferences at the shared off-chip memory level. It is shown that the function-based dynamic instruction scratchpad provides lower WCET estimates, because it eliminates these interferences by design. Thus the function-based dynamic scratchpad eases the analysis while also provides tight WCET estimates.