Analysis of memory latency factors and their impact on KSR1 performance

The KSRI has a shared address space, which spreads over physically distributed memory modules with various latencies. Thus performance depends considerably on the program´s locality of reference and the effectiveness of using prefetch and post-store instructions. This paper analyzes the various memory latency factors which stall the processor during program execution, running on 32-processor system. A suitable model for evaluating these factors is developed for the execution of tiled do-loops with the slice strategy. The benchmark used is a sparse matrix solver. The limited size of the prefetch queue is shown to stall the processor for a long period of time, which reduces the benefit of prefetch considerably. The post-store operation is shown to have a high overhead. However, delaying the post-store operation improved performance considerably