Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

Author

Noguchi, Hiroki ; Ikegami, Kenshin ; Shimomura, Naoharu ; Tetsufumi, Tanamoto ; Ito, Junichi ; Fujita, S.

Author_Institution

Corp. R&D Center, Toshiba Corp., Kawasaki, Japan

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most suitable for large LLC.

Keywords

MRAM devices; cache storage; error correction codes; integrated circuit reliability; low-power electronics; power consumption; ECC; LLC; SRAM; advanced perpendicular STT-MRAM; dual-sensing salvation scheme; embedded DRAM; error-correcting code; high-performance CPU; low-power nonvolatile cache memory; nonvolatile last level cache; readout circuit; total power consumption; Error correction codes; Integrated circuit reliability; Magnetic tunneling; Nonvolatile memory; Random access memory; Resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858403

Filename

6858403