Address-Locking Cache: A Flexible on Chip Memory Implementation for Embedded System

The fast development of mobile devices and commercial electronics brings new challenges to embedded system designers. Meanwhile, on-chip memory in modern embedded systems still not fulfills the needs of applications. In this paper, firstly we review two typical on-chip memory models - cache and scratch pad memory and show their disadvantages. Then we propose an improved cache model called address-locking cache, which supports an innovative cache locking mechanism with high efficiency. It provides flexibility to different applications and overcomes limitations of conventional memory models. Experimental results show that our solution improves the cache hit rate by 20%, and the benefits keep constant with data size increasing. Also some conclusions about cache locking are given.