Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis

As the size and complexity of embedded systems are growing, the area cost and performance of the LSI circuits are becoming more crucial. A critical bottleneck for them is interconnections such as multiplexers (MUXs). Thus, a hardware synthesis technique for reducing MUXs, especially during the earlier design phase, has been demanded. This paper presents a novel MUX reduction technique in high-level synthesis. Our method simultaneously realizes area suppression of both modules and MUXs by selectively sharing costly resources and handles MUX insertion by register-transfer level register retiming so that they do not affect the clock frequency. Experiments demonstrate that our proposed method successfully achieves both the area and clock improvement for practical designs compared with conventional methods.