A 4.68Gb/s belief propagation polar decoder with bit-splitting register file

Author

Youn Sung Park ; Yaoyu Tao ; Shuanghong Sun ; Zhengya Zhang

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A 1.48mm² 1024-bit belief propagation polar decoder is designed in 65nm CMOS. A unidirectional processing reduces the memory size to 45Kb, and simplifies the processing element. A double-column 1024-parallel architecture enables a 4.68Gb/s throughput. A bit-splitting latch-based register file accommodates logic in memory for an 85% density. The architecture and circuit techniques reduce the power to 478mW for an efficiency of 15.5pJ/b/iteration at 1.0V. At 475mV, the efficiency is improved to 3.6pJ/b/iteration for a throughput of 780Mb/s.

Keywords

CMOS logic circuits; decoding; flip-flops; CMOS process; belief propagation polar decoder; bit rate 4.68 Gbit/s; bit rate 780 Mbit/s; bit-splitting latch-based register file; double-column 1024-parallel architecture; power 478 mW; size 65 nm; storage capacity 45 Kbit; voltage 1.0 V; voltage 475 mV; word length 1024 bit; AWGN; Abstracts; Decoding; Registers; Routing; Schedules; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858413

Filename

6858413