Early detection and repair of VRT and aging DRAM bits by margined in-field BIST

Author

Kleveland, Bendik ; Jeong Choi ; Kumala, Jeff ; Adam, Philippe ; Chen, Peng ; Chopra, R. ; Cruz, Alberth ; David, Raluca ; Dixit, Abhishek ; Doluca, Sinan ; Hendrickson, Mark ; Ben Lee ; Ming Liu ; Miller, Michael J. ; Morrison, Matthew ; Na, Byeong C. ;

Author_Institution

MoSys, Inc., Santa Clara, CA, USA

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair.

Keywords

CMOS memory circuits; DRAM chips; ageing; built-in self test; integrated circuit reliability; integrated circuit testing; CMOS technology; VRT repair; aging DRAM bits; chip level; early detection; embedded DRAM; frequency 1.5 GHz; in-field repair; margined in-field BIST; memory cells; size 40 nm; storage capacity 576 Mbit; system availability; variable retention time; word length 72 bit; Aging; Built-in self-test; Computer architecture; Maintenance engineering; Manufacturing; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858414

Filename

6858414