Title :
2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology
Author :
Meterelliyoz, Mesut ; Al-amoody, Fuad H. ; Arslan, Umut ; Hamzaoglu, Fatih ; Hood, Luke ; Lal, Manoj ; Miller, Jeffrey L. ; Ramasundar, Anand ; Soltman, Dan ; Wan Ifar ; Yih Wang ; Zhang, Kai
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
2nd generation 1Gbit 2GHz Embedded DRAM (eDRAM) with 4X lower self refresh power compared to prior generation is developed in 22nm Tri-Gate CMOS technology. Retention time has been improved by 3X (300us@95°C) by process and design optimizations. Source synchronous clocking is integrated in the design to reduce clock power without penalizing bandwidth. Charge pump power is reduced by 4X by employing comparator based regulation. Temperature controlled refresh enables minimum refresh power at all temperature conditions.
Keywords :
CMOS memory circuits; DRAM chips; UHF integrated circuits; charge pump circuits; clocks; comparators (circuits); integrated circuit design; optimisation; 2nd generation embedded DRAM; charge pump power; comparator based regulation; eDRAM; frequency 2 GHz; lower self refresh power; optimization; size 22 nm; source synchronous clocking; storage capacity 1 Gbit; temperature controlled refresh; trigate CMOS technology; Abstracts; CMOS integrated circuits; CMOS technology; Clocks; Optimization; Random access memory; Synchronization;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858415
